A common application of flash EEPROM devices is as a mass data storage subsystem for electronic devices. Such subsystems are commonly implemented as either removable memory cards that can be inserted into multiple host systems or as non-removable embedded storage within the host system. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash EEPROM devices are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Thus flash memory does not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. A typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks, wherein a block contains the smallest number of cells (unit of erase) that are erasable at one time.
In one commercial form, each block contains enough cells to store one sector of user data plus some overhead data related to the user data and/or to the block in which it is stored. The amount of user data included in a sector is the standard 512 bytes in one class of such memory systems but can be of some other size. Because the isolation of individual blocks of cells from one another that is required to make them individually erasable takes space on the integrated circuit chip, another class of flash memories makes the blocks significantly larger so there is less space required for such isolation. But since it is also desired to handle user data in much smaller sectors, each large block is often further partitioned into individually addressable pages that are the basic unit for reading and programming user data. Each page usually stores one sector of user data, but a page may store a partial sector or multiple sectors. A “sector” is used herein to refer to an amount of user data that is transferred to and from the host as a unit.
The subsystem controller in a large block system performs a number of functions including the translation between logical addresses received by the memory sub-system from a host, and physical addresses within the memory cell array. This translation often involves use of intermediate terms for a logical block number (LBN) and logical page. The controller also manages the low-level flash circuit operation through a series of commands that it issues to the flash memory devices via an interface bus. Another function the controller performs is to maintain the integrity of data stored to the subsystem through various means, such as by using an error correction code (ECC).
In flash and some other memory systems, before rewriting a page of data, it must be erased. Therefore, prior to selecting a page of data for storing data, an erased page needs to be found. Consequently, it is of importance to the system to be able to determine as rapidly and conveniently as possible which portions of the memory are in an erased state, either because they have yet to be used or they are a previously written sector that has undergone an erase process. This is not always a straightforward case of just keeping track of blocks in which the controller has instituted an erase operation. For example, in case of a power outage during operation of such a memory circuit, such as when a memory card is removed from a host or a power is lost to a device with an integrated memory, the memory may be caught in the middle of an erase operation, resulting in an incomplete operation. Additional, a sector have been erased, but contains a few corrupted bits, in which simply reading the sector will make it look as if it holds data.
A number of erased sector techniques are known. For example, the content of the sector can just be read; however, aside from the problem of possible corrupted bits, this does not distinguish between a sector that is actually erased and one that happens to have been written with what corresponds to the same data, namely all FFs. One prior art solution, found in U.S. Pat. No. 5,928,370, which is hereby incorporated by reference, is a solution where an ECC engine is used to detect ‘ideal’ erased sectors. The sector data is used to generate a new ECC field, which can be compared to a reference ECC field pre-generated for all FF's. If the ECC fields are the same the, sector is considered to be erased (containing all FF's). However, this still has the problem is that there is a probability of misdetection; additionally, this method does not allow detection of an erased sector with even a single zero bit.